1. Technical Field
The present invention relates generally to semiconductor devices and in particular to routing signals through serially connected circuits of semiconductor devices. Still more particularly the present invention relates to a method and circuit design for enabling both shift path and scan path functionality with a single port LSSD latch designed for scan path functionality only.
2. Description of the Related Art
Operation of semiconductor devices entails the passing of one or more input signals through a series of circuit components that are interconnected in a particular design configuration to generate a response (or output signal) within the device. The path through which the input signal propagates is determined by the type of connectivity among the various logic components within the device, and the value of the signal, as well as the accompanying clock signal.
To ensure proper operation of the semiconductor device, current design and fabrication procedures involves some amounts of post-fabrication testing on all or specific portions of the device to ensure that the components are functioning as desired and yield the correct (or expected) outputs at each stage of the device. For example, semiconductors and other similar devices manufactured with a large number of fuse elements are usually tested post-fabrication. Testing of the device may involve selectively blowing fuses within the device by passing an electrical current through the fuse link, depending on the design of the fuse/device. The fuses that are blown are selected via one or more programming methods, which are generally known to those skilled in the art.
The path utilized for post-fabrication testing is often times different from that utilized during normal signal propagation. In semi-conductor terminology, the normal routing path is referred to as the shift path (from the “shifting” of a propagating “1” or “0” signal in a serial manner from one component to another through the device), while the test path is referred to as the scan path.
Present designs provide a separate scan path along with the shift path for completing the testing of the device. The scan paths are utilized to verify the function of the logic and for any scan preconditioning of the latches done at test. The shift path is utilized for functional operation during fuse blow and fuse readout from the fuse sense latches.
FIG. 1 illustrates a prior art schematic of a portion of the input circuit for a device 100 comprising two levels of serially connected latches. For simplicity of description, the upper level (or register) latch and lower level latch are referred to herein as a latch pair. Also, the first pair of latches, are referred to as the input latches and the second (and subsequent) pair of latches, labeled “Repeatable Scan Latch,” are referred to as internal device latches. Only two pairs of sequential latch pairs are illustrated; However, a complete device may comprise a much larger number of sequentially connected latch pairs similar to the second pair of latches.
As labeled in FIG. 1, the first pair of latches 102A, 102B are full LSSD latches and have dual input ports for both shift and scan chain operations. The second pair of latches, 112A, 112B, however, are scan only latches and thus accommodate only one (scan) path at a time. The two chains of latches (fuse latches 103 and pattern latches 113) are connected in serial fashion, with each latch receiving it's shift input from the previous latch and sending it's shift output to the next latch in the chain.
On the standard full LSSD latch 102A, 102B, two clock ports and two data input ports are provided. One port is used for functional operation (serial shifting in this case) and the other is used for scan operations, a test requirement. Each serial register of latches (LSSD scan latches) comprises a dual-phase latch. The first phase in an LSSD scan latch is called the L1 and is loaded with clock signal ACLK 114. The second phase in the LSSD scan latch is called the L2 and is loaded with signal BCLK 118.
Each latch is configured with an L1 and an L2. Both ports load the L1 of the latch. Only one port may be utilized at a time. The input signals include SCANIN0 104, SHIFTIN 106, SCANIN1 108, and SHIFT 120. Clock signals include CCLK signal 116, ACLK signal 114, and BCLK signal 118. A set of logic gates, AND gate 103 and OR gate 105 are provided to select when the shift input 120 would be allowed to load the L1 during operation.
According to FIG. 1, both the upper level and lower level latches are full LSSD (level sensitive scan design) dual port latches designed to enable separate scan and shift paths as illustrated. A first scan pattern, SCANIN0, is loaded into the upper latch, while a second scan pattern, SCANIN1, is loaded into the lower latch. From the perspective of a scan path, particular types of latches are provided to enable a scan chain evaluation for the device. The upper latch receives a SHIFTIN signal, which triggers the beginning of a shift path. Three clock inputs are also provided to transition the scan and/or shift signal along the device. Each path includes separate clocking domain. The shift/scan path are separated by providing separate shift clock (CCLK) and scan clock (ACLK) signal.
With designs where the functional path matches the scan path, it is possible to use a single data port latch along with OR logic and OR the shift clock (CCLK) and scan clock (ACLK) signals together. However, it may also be required that a long shift path be separated into multiple scan paths. At locations where splitting of the paths is desired, typically a full LSSD latch would be inserted between scan only LSSD latch pairs to provide separate shift and scan ports to the L1.
Particular types of devices, such as electrical fuse (eFuse) devices, for example, are typically designed with separate scan and shift paths, from the perspective of the latch circuitry. In eFuse circuit terminology, the upper level latch 102A is referred to as the fuse sense latch (or fuse latch) and is utilized to read the state of the fuse. Upper level latch is also utilized during the fusing process to enable/disable the blowing of the associated fuse. The lower level latch is referred to as the pattern latch and is utilized to store the redundancy solution calculated for the device. The upper (fuse) latches 103 and lower (pattern) latches 113 are serially connected and may be wired into additional circuitry (e.g., fuse and transistor) in the device.
According to the current art, and as illustrated by FIG. 1, the shift and scan paths were normally split with the addition of a full LSSD latch where the paths had to be split. This addition of a full LSSD latch at each split is difficult to manage in a hierarchical design where the first latch has to be nested completely differently from subsequent latches.
In a next implementation, the shift and scan paths are combined on a scan-only latch by logically ORing the shift clock (CCLK) and scan clock (ACLK) to the latches. This can be done wherever the scan path and functional path share the same serial path through the latches. Removal of the above mentioned requirement was critical for the eFuse design since the electrical design of all the fuse sense latches needed to be the same with the same layout for matching purposes. It was also difficult to do the physical design on a tight pitch with a different latch up front.
One primary concern with current designs is the additional area overhead required because of the need to provide OR gates and other logic within the device for each scan path when a single port latch configuration is utilized. With the dual port LSSD latch configuration, the concern involves additional cost as well as real estate in providing the larger dual port LSSD latches rather than the single port LSSD latches. The current method of providing both scan path and shift path operations for a device also presents problems with embedding particular types of circuitry within an ASIC design. LSSD methodology issues have to be solved to allow for all fuse latches to exist on a single shift register but be broken into multiple scan chains or scan paths. This requires “splitting” the scan and shift paths where required to facilitate ASIC design and test methodology. Using scan only latches and full LSSD latches in the fuse latch chain creates a problem because the electrical characteristic of the internal sense node for fuse are not the same in the two different latch designs, and still requires additional real estate within/on the device.
The present invention recognizes the above inefficiencies that exist in the current design and testing of devices that require both scan path and shift path operations. The invention further recognizes that a method and device that enables efficient combination of scan path and shift path functionality in a single port latch without incurring additional internal overhead costs would be a welcomed improvement. Also desirable is a method and device that enables reduced area overhead along within the device's internal circuitry. These and other benefits are provided by the invention described below.